Major Publication List of Hiroshi Nakashima

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Architecture
Inference Machines (PSI, Multi-PSI, PIM)
1, 2, 3, 4, 5, 6, 8, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20
DSM Parallel Machine (JUMP-1)
27, 29, 34, 35, 39, 48, 49, 52, 55, 61
Volume Rendering Machine (ReVolver)
26, 32, 38, 42, 46, 51, 60, 92
Speculative Memory Access (specMEM)
69, 71, 73, 79, 82
Low-Power/High-Perfromance Cluster (MegaProto, etc.)
98, 105, 111, 116, 125, 134, 135
Supercomputers (T2K Open Supercomputer, etc.)
129, 131, 132, 133, 137, 138, 144, 155, 158, 167, 195
Simulators and Tools (Shaman, BurstScalar, etc.)
77, 80, 83, 85, 86, 87, 90, 91, 94, 95, 97, 99, 100, 104, 107, 108, 110, 114, 115, 117, 120, 121, 122, 124, 126, 140
Computation Reuse
103, 113, 123, 128, 136, 139
Other Architectures
152
Compilers/Language Implementations
Parallel Logic Programming Language (KL1)
7, 18, 31, 33, 58, 59, 64, 65
Parallelizing Compilers
21, 25, 36, 41, 43, 53, 56, 62, 66, 68
Parallel Languages (Orgel, Perl+, MegaScript, Xcrypt, DSL)
72, 81, 84, 89, 101, 106, 118, 119, 130, 142, 143, 146, 147, 149, 156, 157, 162, 164, 165, 166, 173, 175, 177, 179, 184, 188, 200
Software Systems for Grid, Clusters, etc.
78, 88, 93, 102, 109, 112
Parallel Applications
Particle-in-Cell Simulation (OhHelp)
145, 148, 151, 153, 163, 186, 187, 199, 203, 204, 209, 210, 211, 212, 213, 218, 221, 224, 225, 227, 230
Parallel Numerics
159, 160, 169, 170, 172, 174, 176, 178, 180, 181, 182, 183, 185, 189, 190, 191, 192, 194, 196, 197, 198, 201, 205, 206, 207, 214, 216, 217, 219, 220, 222, 226, 229, 231
Parallel Wire Routing (Amon & Amaterous)
22, 30, 40, 50, 54, 75, 76
Gene Analysis, Neural Net, DCS, Graphs, etc.
23, 28, 37, 47, 63, 150, 154, 161, 171, 208, 215, 223, 228
Textbooks, Surveys, Others
9, 24, 44, 45, 57, 67, 70, 74, 96, 127, 141, 168, 193, 202

  1. Kazuo Taki, Minoru Yokota, Akira Yamamoto, Hiroshi Nishikawa, Shunichi Uchida, Hiroshi Nakashima, and Akitoshi Mitsuishi.
    Hardware Design and Implementation of the Personal Sequential Inference Machine (PSI).
    In Proc. Intl. Conf. Fifth Generation Computer Systems 1984, pp. 398-409, November 1984.

  2. Katsuto Nakajima, Hiroshi Nakashima, Minoru Yokota, Kazuo Taki, Shunichi Uchida, Hiroshi Nishikawa, Akira Yamamoto, and Masaki Mitsui.
    Evaluation of PSI Micro-Interpreter.
    In Proc. Compcon Spring 86, pp. 173-177, March 1986.

  3. Kazuo Taki, Hiroshi Nakashima, Katsuto Nakajima, and Morihiro Ikeda.
    Performance and Architectural Evaluation of the PSI Machine.
    In Proc. 2nd Intl. Conf. Architectural Support for Programming Languages and Operating Systems, pp. 128-135, July 1987.

  4. Hiroshi Nakashima and Katsuto Nakajima.
    Hardware Architecture of the Sequential Inference Machine : PSI-II.
    In Proc. 4th IEEE Symp. Logic Programming, pp. 104-113, September 1987.

  5. Hiroshi Nakashima, Katsuto Nakajima, and Kazuo Taki.
    An Experimental Implementation of a Compiler Target Prolog Instruction Set for the PSI Machine and Its Evaluation.
    Trans. Information Processing Society of Japan, Vol. 28, No. 10, pp. 1091-1095, October 1987.
    (in Japanese. ).

  6. Hiroshi Nakashima, Kazuo Taki, Katsuto Nakajima, and Akitoshi Mitsuishi.
    Evaluation of the Personal Sequential Inference Machine PSI---Execution Speed and Performance Analysis of the Hardware Components.
    Trans. Information Processing Society of Japan, Vol. 28, No. 12, pp. 1298-1305, December 1987.
    (in Japanese. ).

  7. Kazuaki Rokusawa, Nobuyuki Ichiyoshi, Takashi Chikayama, and Hiroshi Nakashima.
    An Efficient Termination Detection and Abortion Algorithm for Distributed Processing Systems.
    In Proc. 1988 Intl. Conf. Parallel Processing, Vol. 1, pp. 18-22, August 1988.

  8. Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, and Kazuo Taki.
    A Load Balancing Mechanism for Large Scale Multiprocessor Systems and Its Implementation.
    In Proc. Intl. Conf. Fifth Generation Computer Systems 1988, pp. 978-986, November 1988.

  9. Hiroshi Nakashima.
    VLSI Processors for Symbolic Processing.
    Journal of Information Processing Society of Japan, Vol. 31, No. 4, pp. 486-491, April 1990.
    (in Japanese. ).

  10. Hiroshi Nakashima, Yasutaka Takeda, and Katsuto Nakajima.
    Architecture of the PIM/m Processing Element.
    In Proc. Joint Symposium on Parallel Processing, pp. 145-151, May 1990.
    (in Japanese. ).

  11. Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, and Kiyohiro Furutani.
    A Pipelined Microprocessor for Logic Programming Languages.
    In Proc. 1990 Intl. Conf. Computer Design, pp. 355-359, September 1990.

  12. Yasutaka Takeda, Hiroshi Nakashima, Kanae Masuda, Takashi Chikayama, and Kazuo Taki.
    A Load Balancing Mechanism for Large Scale Multiprocessor Systems and Its Implementation.
    New Generation Computing, Vol. 7, No. 2, pp. 179-195, 1990.

  13. Hirohisa Machida, Hideki Andou, Chikako Ikenaga, Hiroshi Nakashima, Atsushi Maeda, and Masao Nakaya.
    A 1.5 MLIPS 40-bit AI Processor.
    In Proc. Custom Integrated Circuits Conf., pp. 15.3.1-15.3.4, May 1991.

  14. Hiroshi Nakashima.
    Processor Architecture for Logic Programming Languages.
    Ph. d thesis, Kyoto University, August 1991.
    (in Japanese. ).

  15. Kenichi Yasuda, Kiyohiro Furutani, Atsushi Maeda, Shoichi Wakano, Hiroshi Nakashima, Yasutaka Takeda, and Michihiro Yamada.
    An Intelligent Cache Memory Chip Suitable for Logical Inference.
    IEICE Trans., Vol. E74, No. 11, pp. 3796-3802, November 1991.

  16. Hirohisa Machida, Hideki Andou, Kenichi Yasuda, Kiyohiro Furutani, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, and Masao Nakaya.
    A VLSI Chip Set for a Large Scale Parallel Inference Machine: PIM/m.
    In Proc. Custom Integrated Circuits Conf., pp. 30.1.1-30.1.4, May 1992.

  17. Hiroshi Nakashima, Katsuto Nakajima, Seiichi Kondoh, Yasutaka Takeda, Y\=u Inamura, Satoshi Ohnishi, and Kanae Masuda.
    Architecture and Implementation of PIM/m.
    In Proc. Intl. Conf. Fifth Generation Computer Systems 1992, pp. 425-435, June 1992.

  18. Hiroshi Nakashima and Y\=u Inamura.
    An Efficient Message Transfer Mechanism Bypassing Transit Processors.
    In Proc. Joint Symposium on Parallel Processing, pp. 123-130, June 1992.

  19. Hirohisa Machida, Hideki Andou, Chikako Nakanishi, Atsushi Maeda, Hiroshi Nakashima, and Masao Nakaya.
    A 1.5 MLIPS 40-bit AI Processor.
    IEICE Trans., Vol. J76-C-II, No. 1, pp. 8-15, January 1993.
    (in Japanese. ).

  20. Hirohisa Machida, Hideki Andou, Kenichi Yasuda, Kiyohiro Furutani, Yukihiro Ymashita, Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, M. Sakao, and Masao Nakaya.
    A VLSI Chip Set for a Large Scale Parallel Inference Machine: PIM/m.
    IEEE Journal of Solid-State Circuits, Vol. 28, No. 3, pp. 344-351, March 1993.

  21. Atsushi Kubota, Ikuo Miyoshi, Kazuhiko Ohno, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Automatic Parallelizing Compiler for Distributed Memory Parallel Computers---New Algorithms to Improve the Performance of the Inspector/Executor---.
    In Proc. Joint Symposium on Parallel Processing, pp. 47-54, May 1993.
    (in Japanese
    . ).

  22. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A New Technique to Improve Parallel Automated Single Layer Wire Routing.
    In Proc. Performance Evaluation of Parallel Systems, pp. 134-141, November 1993.

  23. Shiho Araki, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, Yutaka Akiyama, and Minoru Kanehisa.
    Application of Parallel DP and A* Algorithm to Multiple Sequence Alignment.
    In Proc. Genome Informatics Workshop IV, pp. 94-102, November 1993.

  24. Hiroshi Nakashima and Shinji Tomita, editors.
    Special Session on Parallel Processing.
    Vol. 35, No. 4, Trans. Information Processing Society of Japan, April 1994.
    (in Japanese. ).

  25. Atsushi Kubota, Ikuo Miyoshi, Kazuhiko Ohno, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallelizing Compiler Technique for Loops with Irregular Accesses---New Algorithms to Improve the Performance of the Inspector/Executor.
    Trans. Information Processing Society of Japan, Vol. 35, No. 4, pp. 444-453, April 1994.
    (in Japanese. ).

  26. Yuji Tsushima, Hideya Akashi, Jin Xidu, Masahiro Susukita, Tomohiro Kuroda, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallel Computer Architecture for Volume Rendering.
    In Proc. Joint Symposium on Parallel Processing, pp. 89-96, May 1994.
    (in Japanese
    . ).

  27. Takeo Hosomi, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Evaluation of Cache Coherence Schemes Based on Update Policy.
    In Proc. Joint Symposium on Parallel Processing, pp. 287-294, May 1994.
    (in Japanese. ).

  28. Jim Torresen, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, and Olav Landsverk.
    Parallel Back Propagation Training Algorithm for MIMD Computer with 2D-Torus Network.
    In Proc. Intl. Conf. Neural Information Processing, Vol. 1, pp. 140-145, October 1994.

  29. Kei Hiraki, Hideharu Amano, Morihiro Kuga, Toshinori Sueyoshi, Tomohiro Kudoh, Hiroshi Nakashima, Hironori Nakajo, Hideo Matsuda, Takashi Matsumoto, and Shin-ichiro Mori.
    Overview of the JUMP-1, an MPP Prototype for General-Purpose Parallel Computations.
    In Proc. Intl. Symp. Parallel Architectures, Algorithms and Networks, pp. 427-434, December 1994.

  30. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallel Slice Maze Router.
    In Proc. Intl. Symp. Fifth Generation Computer Systems, Vol. W6, pp. 67-73, December 1994.

  31. Hiroshi Nakashima and Takashi Chikayama.
    Depth-First Copying Garbage Collection without Extra Stack Space.
    Trans. Information Processing Society of Japan, Vol. 36, No. 3, pp. 697-713, March 1995.
    (in Japanese
    . English version is Tech. Report, 95-0008, Dept. of Information Science, Kyoto Univ., March, 1995 . ).

  32. Yuji Tsushima, Jin Xidu, Akinori Nakayama, Tomotaka Ogino, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    The Parallel Computer for Volume Regering --- ReVolver/C40.
    In Proc. Joint Symposium on Parallel Processing, pp. 11-18, May 1995.
    (in Japanese
    . ).

  33. Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Efficient Message Communication of Concurrent Logic Programming Language KL1 Based on Static Analysis.
    In Proc. Joint Symposium on Parallel Processing, pp. 169-176, May 1995.
    (in Japanese
    . ).

  34. Masahiro Goshima, Shigemitsu Matsumoto, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Virtual Queue: A Message Communication Mechanism for Massively Parallel Computers.
    In Proc. Joint Symposium on Parallel Processing, pp. 225-232, May 1995.
    (in Japanese
    . ).

  35. Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Proposal of Self-Cleanup Cache.
    In Proc. Joint Symposium on Parallel Processing, pp. 265-272, May 1995.
    (in Japanese
    . English version is Tech. Report, 94-0006, Dept. of Information Science, Kyoto Univ., September, 1994. ).

  36. Ikuo Miyoshi, Koji Maeyama, Shin-ya Goto, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    TINPAR: A Parallelizing Compiler for Message-Passing Multiprocessors.
    In Proc. Joint Symposium on Parallel Processing, pp. 51-58, May 1995.
    (in Japanese
    . ).

  37. Jim Torresen, Shin-ichiro Mori, Hiroshi Nakashima, Shinji Tomita, and Olav Landsverk.
    Exploiting Multiple Degrees of BP Parallelism on the Highly Parallel Computer AP1000.
    In Proc. Intl. Conf. Artificial Neural Networks, June 1995.

  38. Yuji Tsushima, Hideya Akashi, Jin Xidu, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallel Computer Architecture for Volume Rendering.
    Trans. Information Processing Society of Japan, Vol. 36, No. 7, pp. 1709-1718, July 1995.
    (in Japanese. ).

  39. Shin-ichiro Mori, Masahiro Goshima, Hiroshi Nakashima, and Shinji Tomita.
    A Proposal of Self-Cleanup Cache.
    In Proc. Intl. Conf. Parallel Architectures and Compilation Techniques, pp. 298-301, July 1995.

  40. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Amon: A Parallel Slice Algorithm for Wire Routing.
    In Proc. Intl. Conf. Supercomputing, pp. 200-209, July 1995.

  41. Atsushi Kubota, Ikuo Miyoshi, Kazuhiko Ohno, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallelizing Compiler Technique for Loops with Irregular Accesses---New Algorithms to Improve the Performance of the Inspector/Executor.
    In Lubomir F. Bic, Alexandru Nicolau, and Mitsuhisa Sato, editors, Parallel Language and Compiler Research in Japan, chapter 13, pp. 313-323. Kluwer Academic Publishers, July 1995.

  42. Yuji Tsushima, Hideya Akashi, Jin Xidu, Masahiro Susukita, Tomohiro Kuroda, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallel Computer Architecture for Volume Rendering.
    In Proc. Intl. Symp. Parallel and Distributed Supercomputing, pp. 261-269, September 1995.

  43. Atsushi Kubota, Ikuo Miyoshi, Koji Maeyama, Shin-ya Goto, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    TINPAR: A Parallelizing Compiler for Message-Passing Multiprocessors.
    In Proc. Intl. Symp. Parallel and Distributed Supercomputing, pp. 214-223, September 1995.

  44. Shinji Tomita and Hiroshi Nakashima.
    Computer Hardware.
    Vol. 6 of Textbook on Information Science.
    Shoko-Do, October 1995.
    (in Japanese. ).

  45. Hideo Aiso, Hajime Iizuka, Hidehiko Tanaka, Shinji Tomita, Toshio Shimada, Hiroshi Nakashima, Ken ichi Yamazaki, and Keiji Hirata.
    Special Talks in 100th Meeting of IPSJ SIGARC.
    Journal of Information Processing Society of Japan, Vol. 36, No. 12, pp. 1166-1178, December 1995.
    (in Japanese. ).

  46. Yuji Tsushima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Parallel Computer Architecture for Volume Rendering.
    In H. Imai, W. F. Wong, and K. F. Loe, editors, Advances in Computing Techniques---Algorithms, Databases and Parallel Processing, pp. 188-205. World Scientific, December 1995.

  47. Jim Torresen, Hiroshi Nakashima, Shinji Tomita, and Olav Landsverk.
    General Mapping of Feed-Forward Neural Networks onto an MIMD Computer.
    In Proc. Intl. Conf. Neural Networks, pp. 1048-1053, November 1995.

  48. Takeo Hosomi, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Performance Evaluation of Cache Coherence Protocols Based on a Directory Scheme.
    Trans. Information Processing Society of Japan, Vol. 37, No. 2, pp. 290-299, February 1996.
    (in Japanese. ).

  49. Shinji Tomita, Kei Hiraki, Hiroshi Nakashima, Shin-ichiro Mori, Takashi Matsumoto, Hideharu Amano, Hironori Nakajo, and Toshinori Sueyoshi.
    Hardware Architecture.
    In Hidehiko Tanaka, Yoichi Muraoka, Masato Amamiya, Nobuo Saito, and Shinji Tomita, editors, The Massively Parallel Processing System JUMP-1, chapter 5, pp. 169-224. OHMSHA Ltd., February 1996.

  50. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Amon2: A Parallel Wire Routing Algorithm on a Torus Network Parallel Computer.
    In Proc. Intl. Conf. Supercomputing, pp. 197-204, May 1996.

  51. Xidu Jin, Yuji Tsushima, Akinori Nakayama, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Architecture of a Special-Purpose Computer for Volume Rendering Based on Pixel Parallel Processing with Restricted View.
    In Proc. Joint Symposium on Parallel Processing, pp. 243-250, June 1996.
    (in Japanese. ).

  52. Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Virtual Queue: A Message Communication Mechanism for Massively Parallel Computers.
    Trans. Information Processing Society of Japan, Vol. 37, No. 7, pp. 1399-1408, July 1996.
    (in Japanese
    . ).

  53. Ikuo Miyoshi, Koji Maeyama, Shin-ya Goto, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    TINPAR: A Parallelizing Compiler for Message-Passing Multiprocessors.
    Trans. Information Processing Society of Japan, Vol. 37, No. 7, pp. 1265-1275, July 1996.
    (in Japanese. ).

  54. Hesham Keshk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Two Phases, Cooperative Detailed/Global Parallel Wire Routing Algorithm.
    Trans. Information Processing Society of Japan, Vol. 37, No. 12, pp. 2376-2389, December 1996.

  55. Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Proposal of Self-Cleanup Cache.
    Trans. Information Processing Society of Japan, Vol. 38, No. 2, pp. 321-331, February 1997.
    (in Japanese. ).

  56. Shin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Generating Optimized Code for Heterogeneous Computing Environment Using Parallelizing Compiler TNPAR.
    In Proc. Joint Symposium on Parallel Processing, pp. 205-212, May 1997.
    (in Japanese
    . ).

  57. Hiroshi Nakashima and Yoshifumi Masunaga.
    The ACM Track as the First Step of Internationalization.
    Journal of Information Processing Society of Japan, Vol. 38, No. 7, pp. 623-624, July 1997.
    (in Japanese. ).

  58. Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Improvement of Message Communication in Concurrent Language.
    In Proc. 2nd Intl. Symp. Parallel Symbolic Computation, pp. 156-164, July 1997.

  59. Kazuhiko Ohno, Masahiko Ikawa, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Efficient Message Communication of Concurrent Logic Programming Language KL1 Based on Static Analysis.
    Trans. Information Processing Society of Japan, Vol. 38, No. 8, pp. 1638-1648, August 1997.
    (in Japanese. ).

  60. Xidu Jin, Yuji Tsushima, Akinori Nakayama, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Architecture of a Special-Purpose Computer for Volume Rendering Based on Pixel Parallel Processing with Restricted View.
    Trans. Information Processing Society of Japan, Vol. 38, No. 9, pp. 1668-1680, September 1997.
    (in Japanese. ).

  61. Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    The Intelligent Cache Controller of a Massively Parallel Processor JUMP-1.
    In Alex Veidenbaum and Kazuki Joe, editors, Innovative Architecture for Future Generation High-Performance Processors and Systems, pp. 116-124. IEEE, October 1997.

  62. Atsushi Kubota, Shougo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
    In Proc. Intl. Symp. High Performance Computing, Vol. 1336, Lecture Notes in Computer Science, pp. 195-204. Springer-Verlag, November 1997.

  63. Jim Torresen, Olav Landsverk, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Exploiting Parallel Computers to Reduce Neural Network Training Time of Real Applications.
    In Proc. Intl. Symp. High Performance Computing, Vol. 1336, Lecture Notes in Computer Science, pp. 405-414. Springer-Verlag, November 1997.

  64. Kazuhiko Ohno, Masahiko Ikawa, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Efficient Goal Scheduling in Concurrent Logic Language Using Type-Based Dependency Analysis.
    In Proc. Asian Computing Science Conf., pp. 268-282, December 1997.

  65. Hiroshi Nakashima and Kazuhiko Ohno.
    Optimizing KLIC with Static Analysis.
    In Proc. Intl. Conf. Applications of Prolog, pp. 18-26, September 1998.

  66. Shin-ya Goto, Atsushi Kubota, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    Optimized Code Generation for Heterogeneous Computing Environment Using Parallelizing Compiler TINPAR.
    In 7th Intl. Conf. Parallel Architecture and Compilation Techniques, pp. 426-433, October 1998.

  67. Hiroshi Nakashima.
    Why Don't We Invest in Speculation?.
    IPSJ Magazine, Vol. 40, No. 2, pp. 195-201, February 1999.
    (in Japanese
    . ).

  68. Atsushi Kubota, Shougo Tatsumi, Toshihiko Tanaka, Masahiro Goshima, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    A Technique to Eliminate Redundant Inter-Processor Communication on Parallelizing Compiler TINPAR.
    International Journal of Parallel Programming, Vol. 27, No. 2, pp. 97-109, 1999.

  69. Takayuki Sato, Kazuhiko Ohno, and Hiroshi Nakashima.
    A Mechanism for Speculative Memory Accesses Following Synchronizing Operations.
    In Proc. Intl. Parallel and Distributed Processing Symp., pp. 145-154, May 2000.

  70. Hiroshi Nakashima, editor.
    Special Issues on Parallel Processing.
    Vol. 41, No. 5, IPSJ Journal, May 2000.
    (in Japanese. ).

  71. Takayuki Sato, Haruyuki Matsuo, Kazuhiko Ohno, and Hiroshi Nakashima.
    specMEM: A Mechanism for Speculative Memory Accesses Following Synchronizing Operations.
    IPSJ Trans. High Performance Computing Systems, Vol. 41, No. SIG 5 (HPS1), pp. 1-14, August 2000.
    (in Japanese
    . ).

  72. Kazuhiko Ohno, Takanori Okano, Shigehiro Yamamoto, and Hiroshi Nakashima.
    Orgel: An Parallel Programming Language with Declarative Communication Streams.
    In 3rd Intl. Symp. High Performance Computing, pp. 344-354, October 2000.

  73. Hiroshi Nakashima, Takayuki Sato, Haruyuki Matsuo, and Kazuhiko Ohno.
    Improved Implementations of the Speculative Memory Access Mechanism specMEM.
    In Alex Veidenbaum and Hiroshi Nakashima, editors, Innovative Architecture for Future Generation High-Performance Processors and Systems, pp. 97-104. IEEE Computer Society, December 2000.

  74. Alex Veidenbaum and Hiroshi Nakashima, editors.
    Innovative Architecture for Future Generation High-Performance Processors and Systems.
    IEEE Computer Society, December 2000.

  75. Kotaro Tanaka, Kazuhiko Ohno, and Hiroshi Nakashima.
    Amaterous: A Parallel Wire Router without Detailed/Global Feedback.
    In Proc. Intl. Conf. Algorithms and Architectures for Parallel Processing, pp. 334-351. World Scientific, December 2000.

  76. Kotaro Tanaka, Kazuhiko Ohno, and Hiroshi Nakashima.
    Amaterous: A Parallel Wire Router with Path Selection Method.
    IPSJ Journal, Vol. 42, No. 4, pp. 732-744, April 2001.
    (in Japanese
    . ).

  77. Shigeru Imafuku, Kazuhiko Ohno, and Hiroshi Nakashima.
    Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors.
    In Proc. 34th Annual Simulation Symp., pp. 219-226, May 2001.

  78. Tomoshige Tashiro, Kazuhiko Ohno, and Hiroshi Nakashima.
    Design and Implementation of the Distributed Computation System WDC.
    In Proc. Joint Symposium on Parallel Processing, pp. 271-278, June 2001.
    (in Japanese. ).

  79. Haruyuki Matsuo, Kazuhiko Ohno, and Hiroshi Nakashima.
    Improvement of the Speculative Memory Access Mechanism: specMEM.
    In Proc. Joint Symposium on Parallel Processing, pp. 181-188, June 2001.
    (in Japanese
    . ).

  80. Shigeru Imafuku, Kazuhiko Ohno, and Hiroshi Nakashima.
    Reference Filtering for Distributed Simulation of Shared Memory Multiprocessors.
    IPSJ Trans. High Performance Computing Systems, Vol. 42, No. SIG 9(HPS3), pp. 93-105, August 2001.
    (in Japanese
    . ).

  81. Kazuhiko Ohno, Shigehiro Yamamoto, Takanori Okano, and Hiroshi Nakashima.
    A Parallel Programming Language based on Declarative Process Network Models.
    IPSJ Trans. High Performance Computing Systems, Vol. 42, No. SIG 12 (HPS4), pp. 95-110, November 2001.
    (in Japanese
    . ).

  82. Haruyuki Matsuo, Kazuhiko Ohno, and Hiroshi Nakashima.
    Improvement of the Speculative Memory Access Mechanism: specMEM.
    IPSJ Journal, Vol. 43, No. 4, pp. 855-865, April 2002.
    (in Japanese
    . ).

  83. Haruyuki Matsuo, Kazuhiko Ohno, and Hiroshi Nakashima.
    Implementation and Evaluation of the Shaman Distributed Simulator for Shared Memory Multiprocessors.
    In Proc. Joint Symposium on Parallel Processing, pp. 111-118, May 2002.
    (in Japanese
    . ).

  84. Yuriko Tonosaki, Takashi Nakada, Kazuhiko Ohno, and Hiroshi Nakashima.
    Design and Implementation of a Parallel Script Language (Perl)+.
    In Proc. Joint Symposium on Parallel Processing, pp. 241-244, May 2002.
    (in Japanese
    . ).

  85. Haruyuki Matsuo, Shigeru Imafuku, Kazuhiko Ohno, and Hiroshi Nakashima.
    Shaman: A Distributed Simulator for Shared Memory Multiprocessors.
    In Proc. 10th IEEE/ACM Intl. Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 347-355, October 2002.

  86. Haruyuki Matsuo, Shigeru Imafuku, Kazuhiko Ohno, and Hiroshi Nakashima.
    Design and Implementation of the Shaman Distributed Simulator of Shared Memory Multiprocessors.
    IPSJ Trans. High Performance Computing Systems, Vol. 44, No. SIG 1(HPS6), pp. 114-127, January 2003.
    (in Japanese
    . ).

  87. Takashi Nakada, Kazuhiko Ohno, and Hiroshi Nakashima.
    High Speed Simulation of High Performance Processor.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 81-88, May 2003.
    (in Japanese
    . ).

  88. Masao Maruyama, Shigehiro Yamamoto, Kazuhiko Ohno, and Hiroshi Nakashima.
    A Parallel Program Debugger Supporting Reverse Execution.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 65-72, May 2003.
    (in Japanese. ).

  89. Yasunori Otsuka, Tasuku Fukano, Hitoshi Nishizato, Kazuhiko Ohno, and Hiroshi Nakashima.
    A Task Parallel Script Languege MegaScript.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 73-76, May 2003.
    (in Japanese
    . ).

  90. Shin ya Honda, Hiroaki Takada, and Hiroshi Nakashima.
    Converting SpecC Description of Software to Implementation Description.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 89-96, May 2003.
    (in Japanese. ).

  91. Shin ya Honda, Hiroaki Takada, and Hiroshi Nakashima.
    Converting SpecC Description of Software to Implementation Description.
    IPSJ Trans. Advanced Computing Systems, Vol. 44, No. SIG 11(ACS3), pp. 236-245, August 2003.
    (in Japanese. ).

  92. Shin-ichiro Mori, Tomoaki Tsumura, Masahiro Goshima, Yasuhiko Nakashima, Hiroshi Nakashima, and Shinji Tomita.
    ReVolver/C40: A Scalable Parallel Computer for Volume Rendering---Design and Implementation---.
    IEICE Trans., Vol. E86-D, No. 10, pp. 2006-2015, October 2003.

  93. Masao Maruyama, Shigehiro Yamamoto, Kazuhiko Ohno, and Hiroshi Nakashima.
    A Parallel Program Debugger Supporting Reverse Execution.
    IPSJ Trans. Advanced Computing Systems, Vol. 45, No. SIG 3(ACS5), pp. 109-121, March 2004.
    (in Japanese. ).

  94. Takashi Nakada and Hiroshi Nakashima.
    Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.
    IPSJ Trans. Advanced Computing Systems, Vol. 45, No. SIG 6(ACS6), pp. 54-65, May 2004.
    (in Japanese
    . ).

  95. Takashi Nakada and Hiroshi Nakashima.
    Design and Implementation of a High Speed Microprocessor Simulator BurstScalar.
    In Proc. 12th IEEE/ACM Intl. Symp. Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 364-372, October 2004.

  96. Hiroshi Nakashima.
    Prominent Books and Articles in the 20th Century---Michael J. Flynn: Very High Speed Computing Systems.
    IPSJ Magazine, Vol. 45, No. 12, p. 1287, December 2004.
    (in Japanese. ).

  97. Toru Takasaki, Takashi Nakada, and Hiroshi Nakashima.
    High Speed Simulation of High Performance Prosessor by Parallel Processing.
    In IPSJ SIG Notes, pp. 7-12, January 2005.
    (in Japanese. IPSJ Yamashita Memorial Award winner).

  98. Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, and Yoshihiko Hotta.
    MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.
    In Proc. WS. High-Performance, Power-Aware Computing (included in Proc. IPDPS 2005), April 2005.

  99. Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Design and Implementation of a Workload Optimized Simulator.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 329-338, May 2005.
    (in Japanese
    . ).

  100. Toru Takasaki, Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Fast Simulation of High Performance Processor with Time Division Parallelization.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 339-348, May 2005.
    (in Japanese
    . ).

  101. Hiroshi Yuyama, Tomoaki Tsumura, and Hiroshi Nakashima.
    Construction of Accurate Task Models for the MegaScript Task Parallel Language.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 43-52, May 2005.
    (in Japanese
    . ).

  102. Masao Maruyama, Tomoaki Tsumura, and Hiroshi Nakashima.
    Parallel Program Debugging Based on Data-Replay.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 61-70, May 2005.
    (in Japanese. ).

  103. Ikuma Suzuki, Yasuki Ikeuchi, Tomoaki Tsumura, Yasuhiko Nakashima, and Hiroshi Nakashima.
    An Evaluation of Reuse with Genetic Algorithms.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 133-142, May 2005.
    (in Japanese. ).

  104. Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, and Hiroshi Nakashima.
    An Efficient Search Algorithm of Worst-Case Cache Flush Timings.
    In Proc. 11th IEEE Intl. Conf. Embedded and Real-time Computing Systems and Applications, pp. 45-52, August 2005.

  105. Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, and Yoshihiko Hotta.
    MegaProto: A Low-Power and Compact Cluster for High-Performance Computing.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG12 (ACS11), pp. 46-61, August 2005.
    (in Japanese
    . ).

  106. Hiroshi Yuyama, Tomoaki Tsumura, and Hiroshi Nakashima.
    Construction of Accurate Task Models for the MegaScript Task Parallel Language.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG12 (ACS11), pp. 181-193, August 2005.
    (in Japanese
    . ).

  107. Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Design and Implementation of a Workload Optimized Simulator.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG12 (ACS11), pp. 98-109, August 2005.
    (in Japanese
    . ).

  108. Toru Takasaki, Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Fast Simulation of High Performance Processor with Time Division Parallelization.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG12 (ACS11), pp. 84-97, August 2005.
    (in Japanese
    . ).

  109. Masao Maruyama, Tomoaki Tsumura, and Hiroshi Nakashima.
    Parallel Program Debugging Based on Data-Replay.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG12 (ACS11), pp. 214-224, August 2005.
    (in Japanese
    . ).

  110. Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Fast Cache Simulation Using Workload Optimization.
    In IPSJ SIG Notes, pp. 97-102, August 2005.
    (in Japanese. IPSJ CS-Region Young Researcher Award winner).

  111. Hiroshi Nakashima, Hiroshi Nakamura, Mitsuhisa Sato, Taisuke Boku, Satoshi Matsuoka, Daisuke Takahashi, and Yoshihiko Hotta.
    MegaProto: 1 TFlops/10 kW Rack Is Feasible Even with Only Commodity Technology.
    In Proc. ACM/IEEE SC|05 Conf., November 2005.
    (http://sc05.supercomputing.org/schedule/pdf/pap183.pdf).

  112. Masao Maruyama, Tomoaki Tsumura, and Hiroshi Nakashima.
    Parallel Program Debugging Based on Data-replay.
    In Proc. 17th IASTED Intl. Conf. Parallel and Distributed Computing and Systems, pp. 151-156, November 2005.

  113. Ikuma Suzuki, Yasuki Ikeuchi, Tomoaki Tsumura, Yasuhiko Nakashima, and Hiroshi Nakashima.
    A Speedup Technique for GA with Reuse.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG 16 (ACS12), pp. 129-143, December 2005.
    (in Japanese
    . ).

  114. Hiroshi Miyamoto, Shinichi Iiyama, Hiroyuki Tomiyama, Hiroaki Takada, and Hiroshi Nakashima.
    An Efficient Search Algorithm of Worst-Case Cache Flush Timings.
    IPSJ Trans. Advanced Computing Systems, Vol. 46, No. SIG 16 (ACS12), pp. 85-94, December 2005.
    (in Japanese
    . ).

  115. Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Design and Implementation of a Workload Specific Simulator.
    In Proc. 39th Annual Simulation Symp., pp. 230-243, April 2006.

  116. Taisuke Boku, Mitsuhisa Sato, Daisuke Takahashi, Hiroshi Nakashima, Hiroshi Nakamura, Satoshi Matsuoka, and Yoshihiko Hotta.
    MegaProto/E: Power-Aware High-Performance Cluster with Commodity Technology.
    In Proc. WS. High-Performance, Power-Aware Computing (included in Proc. IPDPS 2006), April 2006.

  117. Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    MeasuringWorst-Case Performance of Microprocessor by Interruption with Omitting Redundant Execution.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 143-150, May 2006.
    (in Japanese
    . ).

  118. Yusuke Sakaguchi, Kazuhiko Ohno, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    User-Level Extention Scheme for a Task Parallel Script Language.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 447-456, May 2006.
    (in Japanese. ).

  119. Yusuke Sakaguchi, Kazuhiko Ohno, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    User-Level Extention Scheme for a Task Parallel Script Language.
    IPSJ Trans. Advanced Computing Systems, Vol. 47, No. SIG12 (ACS15), pp. 296-307, September 2006.
    (in Japanese
    . ).

  120. Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, and Hiroshi Nakashima.
    Measuring Worst-Case Performance of Microprocessor by Interruption with Omitting Redundant Execution.
    IPSJ Trans. Advanced Computing Systems, Vol. 47, No. SIG12 (ACS15), pp. 159-170, September 2006.
    (in Japanese
    . ).

  121. Hiroshi Nakashima, Masahiro Konishi, and Takashi Nakada.
    An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay.
    In Proc. Intl. Conf. Compilers, Architecture and Synthesis for Embedded Systems, pp. 2-12, October 2006.

  122. Hiroshi Nakashima.
    Architecture Simulation with a Certain Level of Embedded Flavor ---What We Learned from Our Experiments---.
    In IPSJ SIG Notes, pp. 93-96, January 2007.
    (in Japanese
    . Invited Talk).

  123. Tomoaki Tsumura, Yasuki Ikeuchi, Ikuma Suzuki, Hiroshi Nakashima, and Yasuhiko Nakashima.
    Design and Evaluation of an Auto-Memoization Processor.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Networks, pp. 245-250, February 2007.

  124. Masahiro Yano, Toru Takasaki, Takashi Nakada, and Hiroshi Nakashima.
    An Accurate and Efficient Time-Division Parallelization of Cycle Accurate Architectural Simulators.
    In Proc. 40th Annual Simulation Symp., pp. 247-255, March 2007.

  125. Takayuki Imada, Mitsuhisa Sato, Yoshihiko Hotta, Hideaki Kimura, Taisuke Boku, Daisuke Takahashi, Shin'ichi Miura, and Hiroshi Nakashima.
    Power-Performance Evaluation on Ultra-Low Power High-performance Cluster System: MegaProto/E.
    In Proc. COOL Chips X, April 2007.

  126. Masahiro Konishi, Takashi Nakada, Tomoaki Tsumura, Hiroshi Nakashima, and Hiroaki Takada.
    An Efficient Analysis of Worst Case Flush Timings for Branch Predictors.
    IPSJ Trans. Advanced Computing Systems, Vol. 48, No. SIG8 (ACS18), pp. 127-140, May 2007.

  127. Hiroshi Nakashima.
    Thought about the IPSJ: Towards a Society Driving by Young Power---Case Studies and Prospects.
    IPSJ Magazine, Vol. 48, No. 6, pp. 638-641, June 2007.
    (in Japanese. ).

  128. Yusuke Shimazaki, Yasuki Ikeuchi, Tomoaki Tsumura, Hiroshi Nakashima, Hiroshi Matsuo, and Yasuhiko Nakashima.
    Energy Consumption of Auto-Memoization Processor.
    In Proc. FIT2007, pp. 51-54, September 2007.
    (in Japanese
    . 6th Funai Best Paper Award winner).

  129. Hiroshi Nakashima, Mitsuhisa Sato, Taisuke Boku, and Yutaka Ishikawa.
    T2K Open Supercomputer: Its Concept and Architecture.
    France-Japan WS. Petascale Applications, Algorithms and Programming, November 2007.
    (Invited Talk).

  130. Kazuhiko Ohno, Yusuke Sakaguchi, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    A User-level Extension Scheme for a Task Parallel Script Language.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Systems, pp. 274-281, November 2007.

  131. Hiroshi Nakashima, Mitsuhisa Sato, Taisuke Boku, and Yutaka Ishikawa.
    T2K Open Supercomputer: Its Concept and Architecture.
    In PC Cluster Symp., December 2007.
    (in Japanese. Invited Talk).

  132. Hiroshi Nakashima.
    T2K Open Supercomputer and Its Interconnection Network.
    In IEICE Technical Report, December 2007.
    (in Japanese. Invited Talk).

  133. Hiroshi Nakashima.
    T2K Open Supercomputer: Inter-University and Inter-Disciplinary Collaboration on the New Generation Supercomputer.
    In Intl. Conf. Informatics Education and Research for Knowledge-Circulating Society, pp. 137-142, January 2008.
    (Invited Talk).

  134. Hiroshi Nakashima.
    Green High-Performance Computing: Challenge by MegaProto.
    In Proc. 70th IPSJ Conference, March 2008.
    (in Japanese. Invited Talk).

  135. Junichi Hikita, Akio Hirano, and Hiroshi Nakashima.
    Saving 200kW and 200K/year by Power-aware Job/Machine Scheduling.
    In Proc. WS. High-Performance, Power-Aware Computing (included in Proc. IPDPS 2008), April 2008.

  136. Yusuke Shimazaki, Tomoaki Tsumura, Hiroshi Nakashima, Hiroshi Matsuo, and Yasuhiko Nakashima.
    An Energy Control Technique for Auto-Memoization Processor.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 57-64, June 2008.
    (in Japanese. ).

  137. Hiroshi Nakashima.
    Combining the Power of Computer and Computational Sciences to Fly to Peta-Scale ---a Case Study---.
    France-Japan WS. Petascale Applications, Algorithms and Programming, June 2008.
    (Invited Talk).

  138. Hiroshi Nakashima.
    An Introduction to New Supercomputer System in Kyoto University.
    In PC Cluster Symp., July 2008.
    (in Japanese. Invited Talk).

  139. Yusuke Shimazaki, Tomoaki Tsumura, Hiroshi Nakashima, Hiroshi Matsuo, and Yasuhiko Nakashima.
    An Energy Control Technique for Auto-Memoization Processor.
    IPSJ Trans. Advanced Computing Systems, Vol. 1, No. 2, pp. 1-11, August 2008.
    (in Japanese
    . ).

  140. Hiroshi Nakashima, Masahiro Konishi, and Takashi Nakada.
    A Simulation-Based Analysis for Worst Case Delay of Single and Multiple Interruptions.
    IPSJ Trans. System LSI Design Methodology, Vol. 1, pp. 33-47, August 2008.

  141. Hiroshi Nakashima.
    Past and Future of Non-Numerical Parallel Computing.
    Computer Software, Vol. 25, No. 3, pp. 3_43-3_48, September 2008.
    (in Japanese
    . ).

  142. Kazuhiko Ohno, Masaki Matsumoto, Satoshi Katano, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    A Hybrid Scheduling Scheme for Large-Scale Heterogeneous Environments.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Systems, pp. 12-19, November 2008.

  143. Masaki Matsumoto, Satoshi Katano, Takahiro Sasaki, Toshio Kondo, Kazuhiko Ohno, and Hiroshi Nakashima.
    A Hierarchical Scheduling Scheme for Large Scale Heterogeneous Environments.
    IPSJ Trans. Programming, Vol. 2, No. 1, pp. 1-17, January 2009.
    (in Japanese. ).

  144. Yutaka Ishikawa, Kendo Nakajima, Hiroshi Nakashima, and Taisuke Boku.
    New Computation Environment Created by T2K Open Supercomputers.
    J. JSCES, Vol. 14, No. 1, January 2009.
    (in Japanese. ).

  145. Hiroshi Nakashima.
    Knowledge Circulation between High-Performance Computer and Computational Scientists---A Case Study---.
    Joint Workshop of Beijing, Hong Kong and Kyoto on Computational Mathematics, Computer and Systems Sciences, March 2009.
    (Invited Talk).

  146. Hiroshi Nakashima.
    Xcrypt:Highly-Productive Parallel Script Language.
    Intl. WS. Peta-Scale Computing Programming Environment, Languages and Tools, March 2009.
    (Invited Talk).

  147. Tasuku Hiraishi and Hiroshi Nakashima.
    e-science @ Kyoto U.: Highly Productive Script Language.
    In PC Cluster Symp., March 2009.
    (in Japanese. Invited Talk).

  148. Hiroshi Nakashima.
    Performance Evaluation of OhHelp'ed PIC Simulation.
    France-Japan WS. Petascale Applications, Algorithms and Programming, April 2009.
    (Invited Talk).

  149. Tasuku Hiraishi and Hiroshi Nakashima.
    Xcrypt:Highly-Productive Parallel Script Language.
    France-Japan WS. Petascale Applications, Algorithms and Programming, April 2009.
    (Invited Talk).

  150. Suguru Yorifuji, Yusuke Noda, Naoto Kume, Hajime Shimada, Megumi Nakao, Shin-ichiro Mori, Hiroshi Nakashima, and Shinji Tomita.
    An Interactive Simulator with Speculative Execution Based on Continuity in Operation.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 229-238, May 2009.
    (in Japanese. ).

  151. Hiroshi Nakashima, Yohei Miyake, Hideyuki Usui, and Yoshiharu Omura.
    OhHelp: A Scalable Domain-Decomposing Dynamic Load Balancing for Particle-in-Cell Simulations.
    In Proc. Intl. Conf. Supercomputing, pp. 90-99, June 2009.

  152. Jun Yao, Kosuke Ogata, Hajime Shimada, Shinobu Miwa, Hiroshi Nakashima, and Shinji Tomita.
    An Instruction Scheduler for Dynamic ALU Cascading Adoption.
    IPSJ Trans. Advanced Computing Systems, Vol. 2, No. 2, pp. 30-47, July 2009.

  153. Hiroshi Nakashima.
    OhHelp Load Balancer: A Help to PIC Codes for Flying Peta-Scale Sky.
    9th International School for Space Simulations, July 2009.
    (Invited Talk).

  154. Xavier Olive and Hiroshi Nakashima.
    Breaking Symmetries in Distributed Constraint Programming Problems.
    In Proc. Intl. WS. Distributed Constraint Reasoning, pp. 165-169, July 2009.

  155. Hiroshi Nakashima.
    T2K Open Supercomputer at Kyoto U. and Collaborative Research with the Supercomputer.
    Internet Conference 2009, October 2009.
    (in Japanese. Invited Talk).

  156. Kazuhiko Ohno, Masaki Matsumoto, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    An Adaptive Scheduling Scheme for Large-Scale Workflows on Heterogeneous Environments.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Systems, pp. 165-174, November 2009.

  157. Hiroshi Nakashima.
    Progress Report of Xcrypt: What You Can Do Now with the Parallel Script Languate.
    Intl. WS. Peta-Scale Computing Programming Environment, Languages and Tools, February 2010.
    (Invited Talk).

  158. Hiroshi Nakashima.
    T2K Open Supercomputer at Kyoto U. and Collaborative Research on Program Improvement.
    PC Cluster Workshop, February 2010.
    (in Japanese. Invited Talk).

  159. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, and Shinj Wakao.
    Large-scale Micromagnetic Simulation by Using Parallel Fast Multipole Method Specialized for Uniform Brick Elements.
    IPSJ Trans. Advanced Computing Systems, Vol. 3, No. 1, pp. 101-111, March 2010.
    (in Japanese. ).

  160. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Performance Evaluation of Parallel Fast Multipole Accelerated Boundary Integral Equation Method in Electrostatic Field Analysis.
    In Proc. 14th IEEE Conf. Electromagnetic Field Computation, May 2010.
    (doi:10.1109/CEFC.2010.5481427).

  161. Xavier Olive and Hiroshi Nakashima.
    SymDPOP: Adapting DPOP to Exploit Partial Symmetries.
    In Proc. Intl. WS. Distributed Constraint Reasoning, pp. 38-52, May 2010.

  162. Tasuku Hiraishi, Tatsuya Abe, Yohei Miyake, Takeshi Iwashita, and Hiroshi Nakashima.
    Xcrypt: Flexible and Intutive Job-Parallel Script Language.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, May 2010.
    (in Japanese. ).

  163. Hiroshi Nakashima.
    OhHelp Load Balancer for PIC Simulation and Its Library.
    In Proc. Japan Geoscience Union Meeting, May 2010.
    (Invited Talk).

  164. Masaki Matsumoto, Satoshi Katano, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo, and Hiroshi Nakashima.
    An Adaptive Scheduling Scheme for Heterogeneous Environments.
    IEICE Trans. Information and Systems, Vol. J93-D, No. 6, pp. 693-704, June 2010.
    (in Japanese. ).

  165. Kazuhiko Ohno, Akihiro Mita, Masaki Matsumoto, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    Efficient Implementation of Large-scale Workflows based on Array Contraction.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Systems, pp. 153-162, November 2010.

  166. Masaki Matsumoto, Kazuhiko Ohno, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    Dynamic Rescheduling Scheme for Large-Scale Workflows.
    In Proc. Intl. Conf. Parallel and Distributed Computing and Systems, pp. 163-171, November 2010.

  167. Hiroshi Nakashima.
    High-Performance as a Service: Cloudy Supercomputing in Kyoto.
    In Proc. the 9th AEARU Web Technology and Computer Science Workshop, January 2011.
    (Invited Talk).

  168. Jack Dongarra, Pete Beckman, Hiroshi Nakashima, et al.
    The International Exascale Software Project Roadmap.
    Intl. J. High Performance Computer Applications, Vol. 25, No. 1, pp. 3-60, February 2011.

  169. Takeshi Minami, Takeshi Iwashita, Yasuhito Takahashi, and Hiroshi Nakashima.
    Cache-Aware Performance Improvement of Three-Dimensional FDTD Kernel.
    IPSJ Trans. Advanced Computing Systems, Vol. 4, No. 2, pp. 70-83, March 2011.
    (in Japanese. ).

  170. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Large-Scale Micromagnetic Simulations of Perpendicular Recording Head Using the Parallel Fast Multipole Method Specialized for Uniform Brick Elements.
    In Proc. Intl. Magnetics Conf., April 2011.

  171. Xavier Olive and Hiroshi Nakashima.
    Efficient Representation of Constraints and Propagation of Variable-Value Symmetries in Distributed Constraint Reasoning.
    J. Information Processing, Vol. 19, pp. 201-210, May 2011.

  172. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Performance Evaluation of Parallel Fast Multipole Accelerated Boundary Integral Equation Method in Electrostatic Field Analysis.
    IEEE Trans. Magnetics, Vol. 47, No. 5, pp. 1174-1177, May 2011.

  173. Keido Matsushita, Kazuya Taniguchi, Kazuhiko Ohno, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    A Debugging Method Based on Comparison of Execution Trace.
    In Proc. Symp. Advanced Computing Systems and Infrastructures, pp. 152-159, May 2011.
    (in Japanese. ).

  174. Makiko Otani, Kazuo Hirahara, Yasuhito Takahashi, Takane Hori, Mamoru Hyodo, Hiroshi Nakashima, and Takeshi Iwashita.
    Fast Computation of Quasi-Dynamic Earthquake Cycle Simulation with Hierarchical Matrices.
    Procedia Computer Science, Vol. 4, pp. 1456-1465, June 2011.

  175. Masaki Matsumotoa, Kazuhiko Ohno, Takahiro Sasaki, Toshio Kondo, and Hiroshi Nakashima.
    A Dynamic Rescheduling Scheme for Reducing Scheduling Overhead Using Static Information.
    IPSJ Trans. Programming, Vol. 4, No. 3, pp. 55-67, June 2011.
    (in Japanese. ).

  176. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Tadashi Tokumasu, Masafumi Fujita, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Parallel Time-Periodic Finite-Element Method for Steady-State Analysis of Rotating Machines.
    In Proc. Intl. Conf. Computation on Electromagnetic Fields, July 2011.

  177. Hiroshi Nakashima.
    Generator for Library and Application ---Splitting What & How by Domain-Specific Local-View Programming---.
    In Proc. Intl. Cong. Industrial and Applied Mathematics, July 2011.
    (Invited Talk).

  178. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Micromagnetic Simulations of Perpendicular Recording Head Using the Parallel Fast Multipole Method Specialized for Uniform Brick Elements.
    IEEE Trans. Magnetics, Vol. 47, No. 10, pp. 3805-3808, October 2011.

  179. Hiroshi Nakashima.
    Local View Kernels: A New Programming Scheme for Plasma Simulation.
    In Proc. Plasma Conf., November 2011.
    (Invited Talk).

  180. Masatoshi Kawai, Takeshi Iwashita, and Hiroshi Nakashima.
    Parallel Multigrid Poisson Solver Based on Block Red-Black Ordering.
    In Proc. Symp. High-Performance Computing and Computational Science, pp. 107-116, January 2012.
    (in Japanese. Best Paper Award and Excellent Young Resarcher Award winner).

  181. Yasuhito Takahashi, Takeshi Iwashita, Hiroshi Nakashima, Tadashi Tokumasu, Masafumi Fujita, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Parallel Time-Periodic Finite-Element Method for Steady-State Analysis of Rotating Machines.
    IEEE Trans. Magnetics, Vol. 48, No. 2, pp. 1019-1022, February 2012.

  182. Masatoshi Kawai, Takeshi Iwashita, and Hiroshi Nakashima.
    Parallel Multigrid Poisson Solver Based on Block Red-Black Ordering.
    IPSJ Trans. Advanced Computing Systems, Vol. 5, No. 3, pp. 1-10, May 2012.
    (in Japanese. ).

  183. Takeshi Iwashita, Yasuhito Takahashi, and Hiroshi Nakashima.
    Algebraic Block Multi-Color Ordering Method for Parallel Multi-Threaded Sparse Triangular Solver in ICCG Method.
    In Proc. Intl. Parallel and Distributed Processing Symp., pp. 474-483, May 2012.

  184. Tasuku Hiraishi, Tatsuya Abe, Takeshi Iwashita, and Hiroshi Nakashima.
    Xcrypt: a Perl Extension for Job Level Parallel Programming.
    In Proc. Intl. WS. High-performance Infrastructure for Scalable Tools, June 2012.

  185. Masatoshi Kawai, Takeshi Iwashita, Hiroshi Nakashima, and Osni Marques.
    Parallel Smoother Based on Block Red-Black Ordering for Multigrid Poisson Solver.
    In Proc. Intl. Mtng. High-Performance Computing for Computational Science, Vol. 7851, Lecture Notes in Computer Science, pp. 292-299. Springer-Verlag, July 2012.

  186. Yohei Miyake, Hiroshi Nakashima, and Hideyuki Usui.
    Development of a Scalable PIC Simulator and Its Application to Spacecraft-Plasma Interaction Problems.
    In Proc. Intl. Conf. Simulation Technology, pp. 262-267, September 2012.

  187. Yohei Miyake, Hideyuki Usui, Hirotsugu Kojima, and Hiroshi Nakashima.
    Plasma Particle Simulations on Stray Photoelectron Current Flows Around a Spacecraft.
    J. Geophysical Research, Vol. 117, No. A09210, pp. 1-13, September 2012.

  188. Tasuku Hiraishi, Masaru Ueno, Tatsuya Abe, Takeshi Iwashita, and Hiroshi Nakashima.
    Xcrypt in Lisp: A Scripting System for Job Level Parallel Programming in Lisp.
    In Proc. Intl. Lisp Conf., October 2012.

  189. Yasuhito Takahashi, Tadashi Tokumasu, Masafumi Fujita, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Time-Domain Parallel Finite-Element Method for Fast Magnetic Field Analysis of Induction Motors.
    In Proc. 15th Biennial Conf. Electromagnetics Field Compuation, November 2012.

  190. Kazuki Semba, Koji Tani, Takashi Yamada, Takeshi Iwashita, Yasuhito Takahashi, and Hiroshi Nakashima.
    Parallel Performance of Multi-threaded ICCG Solver Based on Algebraic Block Multi-color Ordering In Finite Element Electromagnetic Field Analyses.
    In Proc. 15th Biennial Conf. Electromagneti Field Compuation, November 2012.

  191. Takeshi Minami, Takeshi Iwashita, and Hiroshi Nakashima.
    Temporal and Spatial Tiling Method without Redundant Calculations for Three-Dimensional FDTD Method.
    IPSJ Trans. Advanced Computing Systems, Vol. 6, No. 1, pp. 56-65, January 2013.
    (in Japanese. ).

  192. Kazuki Semba, Takashi Yamada, Takeshi Iwashita, Hiroshi Nakashima, Yasuhito Takahashi, and Takeshi Mifune.
    Effectiveness of Iterative Method with Folded Preconditioning for Practical Finite Element Electromagnetic Field Analyses.
    IEEJ Trans. Industry Applications, Vol. 133, No. 2D, pp. 203-213, February 2013.
    (in Japanese. ).

  193. Hiroshi Nakashima.
    ACCMS, Kyoto U. and Its Resarch Activities.
    PC Cluster Workshop, February 2013.
    (in Japanese. Invited Talk).

  194. Takeshi Iwashita, Akihiro Ida, Masatoshi Kawai, and Hiroshi Nakashima.
    Performance Evaluation of Multi-threaded Iterative Solver on Recent Processors.
    In Proc. 2013 SIAM Conf. Computational Science and Engineering, February 2013.

  195. Hiroshi Nakashima.
    Road Toward Exa-Scale Computing.
    Lecture Series 3, SIG Design Informatics, JSME, March 2013.
    (in Japanese. Invited Talk).

  196. Kazuki Semba, Koji Tani, Takashi Yamada, Takeshi Iwashita, Yasuhito Takahashi, and Hiroshi Nakashima.
    Parallel Performance of Multi-threaded ICCG Solver Based on Algebraic Block Multi-color Ordering In Finite Element Electromagnetic Field Analyses.
    IEEE Trans. Magnetics, Vol. 49, No. 5, pp. 1581-1584, May 2013.

  197. Yasuhito Takahashi, Tadashi Tokumasu, Masafumi Fujita, Takeshi Iwashita, Hiroshi Nakashima, Shinj Wakao, Koji Fujiwara, and Yoshiyuki Ishihara.
    Time-Domain Parallel Finite-Element Method for Fast Magnetic Field Analysis of Induction Motors.
    IEEE Trans. Magnetics, Vol. 49, No. 5, pp. 2413-2416, May 2013.

  198. Takeshi Minami, Motoharu Hibino, Tasuku Hiraishi, Takeshi Iwashita, and Hiroshi Nakashima.
    Performance Improvement of Three-Dimensional Tiled FDTD Kernel Based on Automatic Parameter Tuning.
    In Proc. Intl. Conf. Computation on Electromagnetic Fields, Vol. PC5-12, pp. 1-2, July 2013.

  199. Yohei Miyake and Hiroshi Nakashima.
    Low-Cost Load Balancing for Parallel Particle-in-Cell Simulations with Thick Overlapping Layers.
    In Proc. Intl. Symp. Parallel and Distributed Processing with Applications, pp. 1107-1114, July 2013.

  200. Masaru Ueno, Tasuku Hiraishi, Motoharu Hibino, Takeshi Iwashita, and Hiroshi Nakashima.
    Multilingualization Based on RPC for Job Level Parallel Script Language Xcrypt.
    IPSJ Trans. Programming, Vol. 6, No. 2, pp. 54-68, August 2013.

  201. Kazuki Semba, Koji Tani, Takashi Yamada, Takeshi Iwashita, Yasuhito Takahashi, and Hiroshi Nakashima.
    Parallel Performance of Multi-threaded ICCG Solver in Electromagnetic Finite Element Analyses on the Latest Processors.
    In Proc. Progress In Electromagnetics Research Symp., pp. 979-983, August 2013.

  202. Michel Dayd\'e, Mitsuhisa Sato, Serge Petiton, Hiroshi Nakashima, et al.
    Towards Exascale with the ANR-JST Japanese-French Project FP3C (Framework and Programming for Post-Petascale Computing).
    In Proc. Intl. Conf. Computer Science and Information Technologies, September 2013.

  203. Yohei Miyake, Hideyuki Usui, and Hiroshi Nakashima.
    Full Particle Simulations on Space Plasma Interactions with Scientific Satellite.
    Asia-Pacific Radio Science Conf., September 2013.
    (Invited Talk).

  204. Yohei Miyake, Chris M. Cully, Hideyuki Usui, and Hiroshi Nakashima.
    Plasma Particle Simulations of Wake Formation behind a Spacecraft with Thin Wire Booms.
    J. Geophysical Research, Vol. 118, No. 9, pp. 5681-5694, October 2013.

  205. Yasuhito Takahashi, Tadashi Tokumasu, Koji Fujiwara, Takeshi Iwashita, and Hiroshi Nakashima.
    Parallel TP-EEC Method Based on Phase Conversion for Time-Periodic Nonlinear Magnetic Field Problems.
    In Proc. 16th Biennial Conf. Compuation of Electromagnetics Fields, May 2014.

  206. Masatoshi Kawai, Takeshi Iwashita, and Hiroshi Nakashima.
    SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor.
    In Proc. Intl. Mtng. High-Performance Computing for Computational Science, June 2014.

  207. Takeshi Minami, Motoharu Hibino, Tasuku Hiraishi, Takeshi Iwashita, and Hiroshi Nakashima.
    Automatic Parameter Tuning of Three-Dimensional Tiled FDTD Kernel.
    In Proc. Intl. WS. Automatic Performance Tuning, July 2014.

  208. Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, and Jun Sese.
    Parallelization of Extracting Connected Subgraphs with Common Itemsets.
    IPSJ Trans. Programming, Vol. 7, No. 3, pp. 22-39, July 2014.

  209. Hiroshi Nakashima.
    The First Step to Exa-Scale Era: A Challenge at Kyoto University.
    Cray HPC Seminar, July 2014.
    (Invited Talk).

  210. Hiroshi Nakashima.
    PIC Simulation in Many-Core Era.
    Forum on Advanced Scientific Computing 2014, August 2014.
    (Invited Talk).

  211. Hiroshi Nakashima.
    Manycore Challenge in Kyoto: What We Learned from HPC Programming with KNC.
    Intl. WS. Enhancing Parallel Scientific Applications with Accelerated HPC, September 2014.
    (Invited Talk).

  212. Hiroshi Nakashima.
    Manycore Challenge in Kyoto: What We Learned from HPC Programming with Intel Xeon Phi.
    Intel HPC Developer Conf., November 2014.
    (Invited Talk).

  213. Hiroshi Nakashima.
    Process, Thread and SIMD Parallelism in PIC Method.
    Beam PhysicsWS., November 2014.
    (in Japanese. ).

  214. Takeshi Iwashita, Naokazu Takemura, and Hiroshi Nakashima.
    A Fill-In Strategy for Fast ICCG Solver with SIMD Vectorization.
    In Annual Meeting on Advanced Computing System and Infrastructure, January 2015.

  215. Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, and Jun Sese.
    Reducing Redundant Search using Exception Handling in a Task-Parallel Language.
    In Annual Meeting on Advanced Computing System and Infrastructure, January 2015.
    (Outstanding Research Award and Outstanding Student Research Award winner).

  216. Yasuhito Takahashi, Akira Ahagon, Koji Fujiwara, Takeshi Iwashita, and Hiroshi Nakashima.
    Analysis of Induced Electric Field in Human Body by Utility Power Frequency Magnetic Field Using Parallel Fast Multipole-Accelerated Boundary Element Method.
    IET Science, Measurement & Technology, Vol. 9, No. 2, pp. 178-183, February 2015.

  217. Yasuhito Takahashi, Tadashi Tokumasu, Koji Fujiwara, Takeshi Iwashita, and Hiroshi Nakashima.
    Parallel TP-EEC Method Based on Phase Conversion for Time-Periodic Nonlinear Magnetic Field Problems.
    IEEE Trans. Magnetics, Vol. 51, No. 5, pp. 7001305:1-5, March 2015.

  218. Hiroshi Nakashima.
    Manycore Challenge in Particle-in-Cell Simulation: How to Exploit 1 TFlops Peak Performance for Simulation Codes with Irregular Computation.
    Computers and Electrical Engineering, Vol. 46, pp. 81-94, April 2015.

  219. Masatoshi Kawai, Takeshi Iwashita, and Hiroshi Nakashima.
    SIMD Implementation of a Multiplicative Schwarz Smoother for a Multigrid Poisson Solver on an Intel Xeon Phi Coprocessor.
    In Michel Dayde, Osni Marques, and Kengo Nakajima, editors, High-Performance Computing for Computational Science---VECPAR 2014, Vol. 8969, Lecture Notes in Computer Science, pp. 57-65. Springer-Verlag, May 2015.

  220. Takeshi Iwashita, Naokazu Takemura, Akihiro Ida, and Hiroshi Nakashima.
    A New Fill-In Strategy for IC Factorization Preconditioning Considering SIMD Instructions.
    In Proc. Intl. Symp. Parallel and Distributed Processing with Applications, pp. 37-44, August 2015.

  221. Yuto Kato, Yoshiharu Omura, Yohei Miyake, Hideyuki Usui, and Hiroshi Nakashima.
    Dependencies of the Generation Process of Whistler-Mode Emissions on Temperature Anisotropy of Energetic Electrons in the Earth's Inner Magnetosphere.
    In Proc. 2015 URSI-Japan Radio Science Meeting, September 2015.

  222. Yasuhito Takahashi, Koji Fujiwara, Takeshi Iwashita, and Hiroshi Nakashima.
    Parallel Finite Element Analysis of Rotating Machines Based on Domain Decomposition Considering Nonconforming Mesh Connection.
    IEEE Trans. Magnetics, Vol. 52, No. 3, pp. 7401604:1-4, March 2016.

  223. Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, and Jun Sese.
    Reducing Redundant Search in Parallel Graph Mining using Exception.
    In Proc. IEEE Intl. Parallel and Distributed Processing Symp. WS. (High Level Programming Models and Supporting Environments), pp. 328-337, May 2016.

  224. Hiroshi Nakashima.
    Regularity: A New Important Player in the Game of High-Performance Simulations in Manycore Era.
    In Proc. Intl. Conf. Simulation Technology, pp. 1-8, October 2016.
    (Keynote Speech).

  225. Yuto Kato, Yoshiharu Omura, Yohei Miyake, Hiroshi Nakashima, Hideyuki Usui, and Keiichiro Fukazawa.
    Electron Hybrid Code Simulations with OhHelp Load Balancer for the Study of Relativistic Electron Acceleration in Planetary Magnetospheres.
    In Proc. Intl. Conf. Simulation Technology, October 2016.
    (Outstanding Presentation Award Winner).

  226. Yasuhito Takahashi, Junji Kitao, Koji Fujiwara, Akira Ahagon, Tetsuji Matsuo, Takeshi Iwashita, and Hiroshi Nakashima.
    Steady-State Analysis of Hysteretic Magnetic Field Problems Using Parallel TP-EEC Method.
    In Proc. 17th Biennial Conf. Compuation of Electromagnetics Fields, November 2016.

  227. Hiroshi Nakashima.
    How to Conquer Irregularities to Win the Game vs Accelerators.
    Intel Community Hub, November 2016.
    (Invited Talk).

  228. Shingo Okuno, Tasuku Hiraishi, Hiroshi Nakashima, Masahiro Yasugi, and Jun Sese.
    Parallelization of Extracting Connected Subgraphs with Common Itemsets in Distributed Memory Environment.
    J. Information Processing, Vol. 25, pp. 256-267, February 2017.

  229. Yasuhito Takahashi, Junji Kitao, Koji Fujiwara, Takeshi Iwashita, and Hiroshi Nakashima.
    Time Domain Parallel Finite-Element Method Coupling with Motion for Transient Motor Starting Analysis.
    IEEJ Trans. Power and Energy, Vol. 137, No. 3, March 2017.
    (in Japanese. ).

  230. Hiroshi Nakashima, Yoshiki Summura, Keisuke Kikura, and Yohei Miyake.
    Large Scale Manycore-Aware PIC Simulation with Efficient Particle Binning.
    In Proc. Intl. Parallel and Distributed Processing Symp., May 2017.
    (to appear).

  231. Yasuhito Takahashi, Junji Kitao, Koji Fujiwara, Akira Ahagon, Tetsuji Matsuo, Takeshi Iwashita, and Hiroshi Nakashima.
    Steady-State Analysis of Hysteretic Magnetic Field Problems Using a Parallel Time-Periodic Explicit-Error Correction Method.
    IEEE Trans. Magnetics, Vol. 53, 2017.
    (in press).

Copyright (C) 1997-2014 Hiroshi Nakashima

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